april 2004 dsc-6457/00 1 ? 2004 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. network search engine 32k x 72 entries datasheet brief 75n42102 device description idt provides proven, industry-leading network search engines (nses) that enable and accelerate the intelligent processing of network services in communications equipment. as a part of the complete idt classification subsystem that includes content inspection engines, the idt family of nses delivers high-performance, feature-rich, easy-to-use, integrated search accelerators. the idt 75n42102 nse is a high performance, low cost, full-ternary 32k x 72 entry device. each entry location in the nse has both a data entry and an associated mask entry. the nse devices integrate content addressable memory (cam) technology with high-performance logic. the device can perform lookup operations plus read and write maintenance operations. the idt 75n42102 nse device has a bi-directional bus that is a multiplexed address and data bus that can support up to 200 million sustained searches per second. this device offers the ability to simulta- neously search in mutually exclusive databases substantially increasing the nse search rate. this device can be configured to enable multiple width lookups from 40 to 288 bits wide. the idt 75n42102 requires a 1.5-volt v dd1 supply and a 2.5-volt v dd2 supply. the idt 75n42102 nse utilizes the latest high-performance 1.5v cmos processing technology and is packaged in a jedec standard, thermally enhanced, 304 pin low profile ball grid array. to request the full IDT75N42102 datasheet, please contact your local idt sales representative or call 1-831-754-4555 6457 drw02 optional figure 1.0 asic / compatible nse / sram configuration network interface asic or fpga zbt or sync sram idt 75n42102 network search engine configuration registers and ram control circuits clock cclk 2 phase sram control p r i o r i t y e n c o d e r s i z e l o g i c d e c o d e address matchout reqstb r/w 6457 drw 01 reset command bus request data bus index bus nse request bus nse respons e bus matchin configin asic feedback bypass data array instruction global mask registers result register configout block diagram system configurations the idt nses are designed to fulfill the needs of various types of networking systems. in solutions requiring data searching such as routers, a system configuration as shown in figure 1.0 may be realized. in this configuration, the nse interfaces directly to an asic/ fpga for lookups and routes an index to an associated sram device, which supplies the next hop address via an sram data bus to the asic. the nse provides the required control signals to directly hookup to zbt? or synchronous pipeline burst sram. lookup results can also be fed directly back to the asic/ fpga without the use of external sram. control of the associated handshake signals is provided by all nses to adapt to either configuration.
2 network search engine 32k x 72 entries datasheet brief 75n42102 sram interface the nse provides all required address and control signals for a glueless sram interface. the nse provides a pipelined bypass path for reads or writes to the external sram. the asic/fpga handles the pipelining of the data to and from the sram. registers there are four basic types of registers supported: n configuration registers are used at initialization to define the segmentation of the entries, timing of outputs and the sram interface. n global mask registers are provided to support lookup instructions by masking individual bits during a search. n search result registers are used to store the resulting index of a search from a lookup operation. n reply width registers are used with lookup operations. functional highlights figure 1.1 bus interface the nse utilizes a dual bus interface consisting of the nse request bus and the nse response bus. the nse request bus is comprised of the command bus and the request data bus. the command bus handles the instruction to the nse while the request data bus is the main data path to the nse. the 72 bit bi-directional request data bus functions as a multiplexed address and data bus, which performs the writing and reading of nse entries, as well as presenting lookup data to the device. the nse response bus is comprised of an independent unidirec- tional index bus which drives the result of the lookup (or index) to either an sram device or an asic. in addition to driving the index, the nse response bus also drives the associated sram control signals ( ce / oe , and we ) for either zbt? or synchronous pipeline burst sram devices. data and mask array the nse has data cell entries and associ- ated mask cell entries as shown in fig. 1.1. this combination of data and mask cell entries en- ables the nse to store 0, 1 or x, making it a full ternary network search engine. during a lookup operation, both arrays are used along with a global mask register to find a match to a requested data word. a6457 drw 03 data mask features n n n n n full ternary 32k x 72 bit content addressable memory n n n n n global mask registers n n n n n 40/72/144/288 multiple width lookups n n n n n 200m sustained lookups per second at 72 and 144 width lookups n n n n n dual bus interface n n n n n cascadable to 8 devices with no glue logic or latency penalty n n n n n glueless interface to standard zbt? or synchronous pipelined burst srams n n n n n boundary scan jtag interface (ieee 1149.1compliant) n n n n n 1.5v match power supply n n n n n 2.5v core and i/o power supply command bus the command bus loads the specific instructions into the nse. these include: n read or write a read or write instruction operates on a specified data entry, mask entry, register or external sram. n sram no wait read an sram no wait read is a read instruction to an external sram that can be pipelined within a series of operations and does not require the user to wait for the read to complete before loading the next instruction. n lookup a lookup can be requested in 40-bit, 72-bit, 144-bit or 288-bit widths. n smdl lookup the three smdl lookup instructions offer the ability to simultaneously search in mutually exclusive databases which increases the search rate up to 200 msps.
6.42 3 network search engine 32k x 72 entries datasheet brief 75n42102 signal descriptions pin function i/o description nse request bus: request strobe input this input signifies a valid input request and signals the start of an nse operation cycle. command bus input defines the instruction to be performed by the nse and selects global mask registers and search result registers. request data bus input/output three state the request data bus is a multiplexed address/data bus used to perform reads (and writes) from (to) the nse, and to present search data for lookups. nse response bus: index bus output three state this bus is used to drive the address of an external sram, or feedback lookup result information directly to the nse's asic/fpga. the index bus contains the encoded location at which the compare was found. chip enable/ output enable output three state this signal is driven along with the index bus. it is connected to the ce input pin of a zbt sram or to the oe pin of a pbsram. write enable output three state this signal is driven along with the index bus. it is used to assert the we pin of an external sram. it is active for sram write operations. read acknowledge output this signal is sent back when the data is read from the nse on the request data bus, or when the data being read from the associated external sram. match acknowledge output this is signal is sent with the index. it will be driven low if there was no match, high if a match was found. valid lookup bit output this signal is sent with the index. it will be driven high upon the completion of a lookup, even if the lookup did not result in a hit. clock and initialization: clock input input all inputs and outputs are referenced to the positive edge of this clock. clock phase enable input this signal is used to generate an internal clock at ? the frequency of the input clock. reset input this pin will force all outputs to a high impedence condition, as well as clearing the nse enable bit. depth expansion: configuration in input configures the device id at power up. configuration out output configures the device id at power up. match input input the match input signal is driven by all upstream match output signals. this indicates to all down stream nses that a hit in a higher priority nse has occurred. match output output the match output signal signifies that a match has occurred in the nse. the signal is fed into a match input line of all lower priority nse(s). 64 57 tbl 01
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